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TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
Rev. 01 -- 18 January 2007 Product data sheet
1. General description
The GreenChip II is the second generation of controller ICs intended for green flyback Switched Mode Power Supplies (SMPS). Its high level of integration allows the design of a cost effective power supply with a very low number of external components. The TEA1532BT; TEA1532CT can also be used in fixed frequency, Continuous Conduction Mode (CCM) converter designs for low voltage and high current applications. At low power (standby) levels the system operates in cycle skipping mode which minimizes the switching losses during standby. The special built-in green functions allow the efficiency to be optimum at all power levels. This holds for quasi-resonant operation at high power levels, as well as fixed frequency operation with valley switching at medium power levels. At low power (standby) levels, the system operates in cycle skipping mode with valley detection. The proprietary high voltage BCD800 process makes direct start-up possible from the rectified universal mains voltage in an effective and energy efficient way. A second low voltage, Bipolar CMOS (BICMOS) IC is used for accurate, high speed protection functions and control. The TEA1532BT; TEA1532CT enables highly efficient and reliable supplies to be designed easily.
2. Features
2.1 Distinctive features
I I I I Universal mains supply operation (70 V to 276 V AC) High level of integration resulting in a very low external component count Fixed frequency Continuous Conduction Mode (CCM) operation capability Quasi-Resonant (QR) Discontinuous Conduction Mode (DCM) operation capability
2.2 Green features
I Valley or zero voltage switching for minimum switching losses in QR operation I Cycle skipping mode at very low loads; input power < 300 mW at no-load operation for a typical adapter application I On-chip start-up current source
2.3 Protection features
I Safe restart mode for system fault conditions I Zero current switch-on in QR mode
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
I I I I I I
Undervoltage protection (fold back during overload) IC OverTemperature Protection (OTP) (latched) Low and adjustable OverCurrent Protection (OCP) trip level Soft (re)start Mains voltage-dependent operation-enabling level TEA1532CT: general purpose input for latched or safe restart protection and timing, e.g. to be used for OverVoltage Protection (OVP), output short-circuit protection or system OTP I TEA1532BT: general purpose input for latched protection and timing, e.g. to be used for OVP, output short-circuit protection or system OTP I Brown-out protection
3. Applications
I Adapters and open frame flyback power supplies. The device can also be used in all applications that demand an efficient and cost-effective solution up to 250 W.
4. Ordering information
Table 1. Ordering information Package Name TEA1532BT TEA1532CT SO8 Description plastic small outline package; 8 leads; body width 3.9 mm Version SOT96-1 Type number
TEA1532BT_TEA1532CT_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 18 January 2007
2 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
5. Block diagram
VCC
1
SUPPLY MANAGEMENT DCM AND CCM DETECTION
START-UP CURRENT SOURCE VALLEY
8
DRAIN
internal UVLO start supply GND 2 S1 Vmains(oper)(en)
clamp
5 OSCILLATOR LOGIC
80 mV
DEM
SLOPE COMPENSATION DRIVER Osc_Rdy Duty_Max 4 LOGIC
-50 mV
7
DRIVER
Isc/t
-1 POWER-ON RESET
5.6 V
CTRL
Istartup(soft) S Q LEB blank UVLO R Q OCP
0.5 V
soft start S2
control detect
MAXIMUM ON-TIME PROTECTION 6 DCM and CCM BROWN-OUT PROTECTION SENSE
0.63 V
S3
(1) 2.5 V
PROTECT
3
300
Ich S
5.6 V
Q
Idch
3V
protect detect
OVERTEMPERATURE PROTECTION
VCC < 4.5 V
R
Q
TEA1532BT TEA1532CT
coa047
(1) Switch S3 is not controlled in the TEA1532BT (fixed as drawn).
Fig 1. Block diagram
TEA1532BT_TEA1532CT_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 18 January 2007
3 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
6. Pinning information
6.1 Pinning
VCC GND PROTECT CTRL
1 2 3 4
001aaf068
8
DRAIN
7 DRIVER TEA1532BT TEA1532CT 6 SENSE 5 DEM
Fig 2. Pin configuration: TEA1532BT and TEA1532CT (SOT96-1)
6.2 Pin description
Table 2. Symbol VCC GND PROTECT CTRL DEM SENSE DRIVER DRAIN Pin description Pin 1 2 3 4 5 6 7 8 Description supply voltage ground protection and timing input control input input from auxiliary winding for demagnetization timing programmable current sense input MOSFET gate driver output drain of the external MOS switch, input for start-up current and valley sensing
7. Functional description
The TEA1532BT; TEA1532CT is a controller for a compact flyback converter with the IC situated on the primary side. An auxiliary winding of the transformer provides demagnetization detection and powers the IC after start-up; see Figure 3.
TEA1532BT_TEA1532CT_1
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Product data sheet
Rev. 01 -- 18 January 2007
4 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
Vi CVIN
1 CVCC 2 3 4
8 7 6 5
TEA1532BT TEA1532CT
coa048
Fig 3. Basic configuration
The TEA1532BT; TEA1532CT can operate in multi modes; see Figure 4.
f (kHz) Cycle skip 125
fixed
FF-CCM
QR
P (W)
coa049
Fig 4. Multi mode and FF-CCM operation
In QR mode, the next converter stroke is started only after demagnetization of the transformer current (zero current switching), while the drain voltage has reached the lowest voltage to minimize switching losses (green function). The primary resonant circuit of primary inductance and drain capacitor ensures this quasi-resonant operation. The design can be optimized in such a way that zero voltage switching can extend over most of the universal mains range.
TEA1532BT_TEA1532CT_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 18 January 2007
5 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
To prevent very high frequency operation at lower loads, the quasi-resonant operation changes smoothly in fixed frequency Pulse Width Modulation (PWM) control. In fixed frequency continuous conduction mode, which can be activated by grounding pin DEM, the internal oscillator determines the start of the next converter stroke. In both operating modes, a cycle skipping mode is activated at very low power (standby) levels.
7.1 Start-up, mains enabling operation level and undervoltage lock out
Refer to Figure 9 and Figure 10. Initially, the IC is self supplying from the rectified mains voltage via pin DRAIN. Supply capacitor CVCC (at pin 1) is charged by the internal start-up current source to a level of about 4 V or higher, depending on the drain voltage. Once the drain voltage exceeds the Vmains(oper)(en) (mains-dependent operation-enabling level), the start-up current source will continue charging capacitor CVCC (switch S1 will be opened); see Figure 1. The IC will activate the power converter as soon as the voltage on pin VCC passes the Vstartup level. At this moment the IC supply from the high voltage pin is stopped (green function). The IC supply is taken over by the auxiliary winding of the flyback converter. The moment the voltage on pin VCC drops below Vth(UVLO) (undervoltage lock out), the IC stops switching and performs a safe restart from the rectified mains voltage. In the safe restart mode the driver output is disabled and pin VCC voltage is recharged via pin DRAIN.
7.2 Supply management
All (internal) reference voltages are derived from a temperature compensated, on-chip band gap circuit.
7.3 Oscillator
The fixed frequency of the oscillator is set by an internal current source and capacitor.
7.4 Cycle skipping
At very low power levels a cycle skipping mode activates. An internal control voltage (Vsense(max)) lower than 25 mV will inhibit switch-on of the external power MOSFET until this voltage increases to a higher value; see Figure 5.
7.5 Current control mode
Current control mode is used for its good line regulation behavior. The primary current is sensed across an external resistor and compared with the internal control voltage. The driver output is latched in the logic, preventing multiple switch-on. The internal control voltage is inversely proportional to the external pin CTRL voltage, with an offset of 1.5 V. This means that a voltage range from 1 V to approximately 1.5 V on pin CTRL will result in an internal control voltage range from 0.5 V to 0 V (a high external control voltage results in a low duty cycle).
TEA1532BT_TEA1532CT_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 18 January 2007
6 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
Vsense(max) (V)
coa016
0.52 V cycle skip active
25 mV 1V (typ) 1.5 V (typ) VCTRL (V)
Fig 5. The Vsense(max) voltage as a function of VCTRL
7.6 OverCurrent Protection (OCP)
The primary peak current in the transformer is measured accurately cycle-by-cycle using the external sense resistor Rsense. The OCP circuit limits the voltage on pin SENSE to an internal level equal to 1.5 V - VCTRL (see also Section 7.5). The OCP detection is suppressed during the leading edge blanking period, tleb, to prevent false triggering caused by the switch-on spikes.
7.7 Demagnetization (QR operation)
The system will be in Discontinuous Conduction Mode (DCM) (QR operation) when resistor RDEM is applied. The oscillator will not start a new primary stroke until the previous secondary stroke has ended. Demagnetization features a cycle-by-cycle output short-circuit protection, which immediately reduces the frequency (longer off-time), thereby reducing the power level. Demagnetization recognition is suppressed during the first tsup(xfmr_ring) time (typical 1.5 s). This suppression may be necessary in applications where the transformer has a large leakage inductance and at low output voltages or start-up.
7.8 Valley switching
Refer to Figure 6. A new cycle starts when the power switch is activated. After the on-time (determined by the sense voltage and the internal control voltage), the switch is opened and the secondary stroke starts. After the secondary stroke, the drain voltage shows an 1 oscillation with a frequency of approximately ----------------------------------------2 x x L p x Cd where Lp is the primary self inductance of the transformer and Cd is the capacitance on the drain node. As soon as the oscillator voltage is high again and the secondary stroke has ended, the circuit waits for the lowest drain voltage before starting a new primary stroke. This method is called valley detection. Figure 6 shows the drain voltage, valley signal, secondary stroke signal and the oscillator signal.
TEA1532BT_TEA1532CT_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 18 January 2007
7 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
In an optimum design, the reflected secondary voltage on the primary side will force the drain voltage to zero. Thus, zero voltage switching is possible, preventing large capacitive 1 2 switching losses P = -- x C x V x f , and allowing high frequency operation, which 2 results in small and cost-effective magnetics.
primary stroke
secondary stroke
secondary ringing
drain
valley
secondary stroke
(2)
(1)
oscillator
mgu235
(1) Start of new cycle at lowest drain voltage. (2) Start of new cycle in a classical PWM system at high drain voltage.
Fig 6. Signals for valley switching
7.9 Continuous Conduction Mode (CCM)
It is also possible to operate the IC in the so-called Fixed Frequency Continuous Conduction Mode (FF CCM). This mode is activated by connecting pin DEM to ground and connecting pin DRAIN to the rectified VI voltage; see Figure 12.
7.10 Adjustable slope compensation
A slope compensation function has been added at pin CTRL; see Figure 7. The slope compensation function prevents sub-harmonic oscillation in CCM at duty cycles over 50 %. The CTRL voltage is modulated by sourcing a (non-constant) current out of pin CTRL and adding a series resistor Rslopecomp. This increases the CTRL voltage proportionally with the on-time, which therefore limits the OCP level. Thus, a longer on-time results in a higher CTRL voltage. However, this increase in CTRL voltage will actually decrease the on-time. Slope compensation can be adjusted by changing the
TEA1532BT_TEA1532CT_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 18 January 2007
8 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
value of Rslopecomp. Slope compensation prevents modulation of the on-time (duty cycle) while operating in FF CCM. A possible drawback of sub-harmonic oscillation can be output voltage ripple.
slope compensation current
Rsc
CTRL 4
-1 5.6 V
RCTRL
control detect
0.63 V
001aaa830
Fig 7. Slope compensation
7.11 Minimum and maximum on-time
The minimum on-time of the SMPS is determined by the Leading Edge Blinking (LEB) time (typically 400 ns). The IC limits the on-time to a maximum time, which is dependent on the mode of operation: QR mode: When the system requires an `on-time' of more than 25 s, a fault condition is assumed (e.g. CVCC removed). The IC stops switching and enters the safe restart mode. CCM: The driver duty cycle is limited to 70 %. So the maximum on-time is correlated to the oscillator time, which results in an accurate limit of the minimum input voltage of the flyback converter.
7.12 Soft start-up (pin SENSE)
To prevent transformer rattle at start-up or during hiccup, the transformer peak current is slowly increased by the soft start function. This can be achieved by inserting a resistor and a capacitor between pin SENSE (pin 6) and sense resistor Rsense. An internal current source charges the capacitor to VSENSE = Istartup(soft) x Rss (about 0.5 V maximum). The start level and the time constant of the increasing primary current level can be adjusted externally by changing the values of Rss and Css. V sense ( max ) - ( I startup ( soft ) x R ss ) I DM = -------------------------------------------------------------------------------------R sense = R ss x C ss
TEA1532BT_TEA1532CT_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 18 January 2007
9 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
The charging current Istartup(soft) will flow as long as the voltage on pin SENSE is below approximately 0.5 V. If the voltage on pin SENSE exceeds 0.5 V, the soft start current source will start limiting current Istartup(soft). At Vstartup, the Istartup(soft) current source is completely switched off; see Figure 8. Since the soft start current is supplied from pin DRAIN, the Rss value will not affect VCC current during start-up.
Iss
0.5 V
start-up 6 SENSE Rss
Vocp
Css
Rsense
mgu237
Fig 8. Soft start-up
7.13 Control pin protection
If the pin CTRL becomes open-circuit or is disconnected, a fault condition is assumed and the converter will stop switching immediately. Operation recommences when the fault condition is removed.
7.14 PROTECT and timing input
The PROTECT input (pin 3) is a multi-purpose (high-impedance) input, which can be used to switch off the IC and create a relatively long timing function. As soon as the voltage on this pin rises above 2.5 V, switching stops immediately. For the timing function, a current of typically 50 A flows out of pin PROTECT and charges an external capacitor until the activation level of 2.5 V is reached. This current source is only activated when the converter is not in regulation, which is detected by the voltage on pin CTRL (VCTRL < 0.63 V). A (small) discharge current is also implemented to ensure that the capacitor is not charged, for example, by spikes. A MOSFET switch is added to discharge the external capacitor and ensure a defined start situation. For the TEA1532CT, the voltage on pin CTRL determines whether the IC enters latched protection mode, or safe restart protection mode:
* When the voltage on pin CTRL is below 0.63 V, the IC is assumed to be out of
regulation (e.g. the control loop is open). In this case activating pin PROTECT (VPROTECT > 2.5 V) will cause the converter to stop switching. Once VCC drops below Vth(UVLO), capacitor CVCC will be recharged and the supply will restart. This cycle will be repeated until the fault condition is removed (safe restart mode).
* When the voltage on pin CTRL is above 0.63 V, the output is assumed to be in
regulation. In this case activating pin PROTECT (VPROTECT > 2.5 V), by external means, will activate the latch protection of the IC: The voltage on pin VCC will cycle between Vstartup and Vth(UVLO), but the IC will not start switching again until the latch
TEA1532BT_TEA1532CT_1 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 18 January 2007
10 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
protection is reset. The latch is reset as soon as VCC drops below 4.5 V (typical value) (this only occurs when the mains has been disconnected). The internal overtemperature protection will also trigger this latch; see also Figure 1. For the TEA1532BT the IC always enters the latched mode protection independent of the voltage on pin CTRL. A voltage higher than 3 V on pin PROTECT will always latch the IC. This is independent of the state or the version of the IC.
7.15 OverTemperature Protection (OTP)
The IC provides accurate OTP. The IC will stop switching when the junction temperature exceeds the thermal shutdown temperature. When VCC drops to Vth(UVLO), capacitor CVCC will be recharged to the Vstartup level, however switching will not restart. Subsequently, VCC will drop again to Vth(UVLO), etc. Operation only recommences when VCC drops below a level of about 4.5 V (typically, when Vmains is disconnected for a short period).
7.16 Brown-out protection
During the so called brown-out test, the input voltage is slowly decreased. Since the on-time depends on Vi, long on-times at low Vi can damage the (external) power device. This is prevented by stopping the converter when the input voltage drops too low. When the voltage on pin DEM drops below -50 mV during the on-time (QR mode), the maximum on-time is set to 25 s. The maximum on-time will be reached while Vi is low. Subsequently, the IC stops switching and VCC drops below Vth(UVLO). Capacitor CVCC will only be recharged and the supply will restart only when voltage VI is high enough (Vmains(oper)(en), also see Section 7.1). In addition to this, a VI level at which the converter has to enter a safe restart can be set with a demagnetization resistor. During the primary stroke, the rectified mains input voltage is measured by sensing the current drawn from pin DEM. This current depends on the mains voltage, according to the following equation: V aux N x V mains I DEM -------------- --------------------------R DEM R DEM N aux Where: N = ----------- (ratio of the number of auxiliary to the number of primary windings) Np The latter function requires an on-time of at least 2 s. This on-time ensures that a reliable demagnetization current can be measured. When pin DEM is grounded (CCM), the brown-out protection is disabled. In this case the duty cycle is limited to 0.7, so at low mains voltage the on-time is limited and therefore the dissipation in the FET is limited.
7.17 Driver
The driver circuit to the gate of the power MOSFET has a current sourcing capability of typically 170 mA and a current sink capability of typically 700 mA. This permits fast turn-on and turn-off of the power MOSFET for efficient operation.
TEA1532BT_TEA1532CT_1 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 18 January 2007
11 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
A low driver source current has been chosen to limit the V/t at switch-on. This reduces ElectroMagnetic Interference (EMI) and also limits the current spikes across Rsense.
8. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Voltages VCC VPROTECT VCTRL VDEM VSENSE VDRAIN Currents ICTRL IDEM ISENSE IDRIVER IDRAIN General Ptot Tstg Tj ESD VESD electrostatic discharge voltage human body model machine model
[1] [2]
Parameter supply voltage voltage on pin PROTECT voltage on pin CTRL voltage on pin DEM voltage on pin SENSE voltage on pin DRAIN current on pin CTRL current on pin DEM current on pin SENSE current on pin DRIVER current on pin DRAIN total power dissipation storage temperature junction temperature
Conditions continuous continuous current limited current limited
Min -0.4 -0.4 -0.4 -0.4 -0.4
Max +20 +5 +5 +650 50 +250 +10 +2 5 0.5 +150 +145
Unit V V V V V V mA A mA A mA W C C
d < 10 %
-1000 -1
d < 10 %
-0.8 -
Tamb < 70 C
-55 -20
class 1 pins 1 to 7 pin 8 (DRAIN)
[1] [1] [2]
-
2000 1500 200
V V V
Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. Equivalent to discharging a 200 pF capacitor through a 0.75 H coil and a 10 resistor.
9. Thermal characteristics
Table 4. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions in free air Typ 150 Unit K/W
TEA1532BT_TEA1532CT_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 18 January 2007
12 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
10. Characteristics
Table 5. Symbol IDRAIN Characteristics Parameter current on pin DRAIN Conditions VDRAIN > 100 V VCC = 0 V with auxiliary supply VBR Vmains(oper)(en) breakdown voltage mains-dependent operation-enabling voltage start-up voltage undervoltage lockout threshold voltage hysteresis voltage high charging current low charging current restart current operating supply current threshold voltage on pin DEM continuous conduction mode detection threshold voltage negative clamp voltage positive clamp voltage transformer ringing suppression time minimum on-time maximum on-time maximum duty cycle oscillator frequency VCTRL < 1 V QR mode IDEM = -500 A IDEM = 250 A at start of secondary stroke Vstartup - Vth(UVLO) VDRAIN > 100 V; VCC < 3 V VDRAIN > 100 V; 3 V < VCC < Vth(UVLO) VDRAIN > 100 V; Vth(UVLO) < VCC < Vstartup no load on pin DRIVER 1.0 650 60 1.2 100 1.4 300 100 mA A V V Min Typ Max Unit
Start-up current source (pin DRAIN)
Supply voltage management (pin VCC) Vstartup Vth(UVLO) Vhys Ich(high) Ich(low) Irestart ICC(oper) 10.3 8.1 2.0 -1.2 -1.2 -650 1.1 11 8.7 2.3 -1 -0.75 -550 1.3 11.7 9.3 2.6 -0.8 -0.45 -450 1.5 V V V mA mA A mA
Demagnetization management (pin DEM) Vth(DEM) Vth(det)(CCM) 50 -80 80 -50 110 -20 mV mV
VCL(neg) VCL(pos) tsup(xfmr_ring)
-0.5 0.5 1.1
-0.45 0.7 1.5
-0.40 0.9 1.9
V V s
Pulse width modulator ton(min) ton(max) max Oscillator fosc 100 125 150 kHz 20 67 tleb 25 70 30 73 ns s %
TEA1532BT_TEA1532CT_1
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Product data sheet
Rev. 01 -- 18 January 2007
13 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
Table 5. Symbol Vmin(max) Vmax(min) Isc/t
Characteristics ...continued Parameter minimum voltage (maximum duty cycle) maximum voltage (minimum duty cycle) slope compensation current detection voltage on pin CTRL trip voltage latch trip voltage latch reset voltage on pin VCC charge current discharge current valley recognition voltage change with time valley recognition to switch-on delay time maximum sense voltage propagation delay leading edge blanking time soft startup current brownout protection current brownout protection enable time VSENSE < 0.5 V A constant Iprot(bo) is drawn from pin DEM.
[3] [2] [1]
Conditions
Min -1.2 0.56
Typ 1.0 1.5 -1 0.63
Max -0.8 0.70
Unit V V A/s V
Duty cycle control (pin CTRL)
VCTRL(detect)
Protection and timing input (pin PROTECT) Vtrip Vtrip(latch) VVCC(latch)(reset) Ich Idch (V/t)vrec 2.37 2.85 VPROTECT < 2.3 V VCTRL < 0.63 V -57 -43 2.5 3 4.5 -50 100 2.63 3.15 -43 +43 V V V A nA V/s
Valley switch (pin DRAIN)
td(vrec-swon)
-
150
-
ns
Overcurrent and winding short-circuit protection (pin SENSE) Vsense(max) tPD tleb Istartup(soft) Iprot(bo) ten(prot)bo V/t = 0.1 V/s V/t = 0.5 V/s 0.48 330 45 -68 1.5 0.52 140 400 60 -60 2 0.56 185 470 75 -52 2.5 V ns ns A A s
Brown-out protection (pin DEM)
TEA1532BT_TEA1532CT_1
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Product data sheet
Rev. 01 -- 18 January 2007
14 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
Table 5. Symbol Isource Isink
Characteristics ...continued Parameter source current sink current Conditions VCC = 9.5 V; VDRIVER = 2 V VCC = 9.5 V VDRIVER = 2 V VDRIVER = 9.5 V 400 300 700 11.5 12 mA mA V Min Typ -170 Max -88 Unit mA
Driver (pin DRIVER)
Vo(max)
maximum output voltage maximum protection level temperature protection level hysteresis temperature
VCC > 12 V
Temperature protection Tpl(max) Tpl(hys) 130 VCC > 2 V 140 8 150 C C
[1] [2] [3]
TEA1532CT: safe restart; TEA1532BT: latch. Guaranteed by design. Vi detection level. Set by the demagnetization resistor RDEM; see Section 7.16.
11. Application information
A converter with the TEA1532BT; TEA1532CT consists of an input filter, a transformer with a third winding (auxiliary), and an output stage with a feedback circuit. Capacitor CVCC buffers the IC supply voltage, which is powered via the internal current source, that is connected to the rectified mains during start-up and, via the auxiliary winding, during operation. A sense resistor Rsense converts the primary current into a voltage at pin SENSE. The value of Rsense defines the maximum primary peak current. Figure 9 shows a flyback configuration using the discontinuous conduction mode. Pin PROTECT is used in this example for external overvoltage protection and open loop or output short-circuit protection. If this pin is not used, it must be tied to ground. Figure 12 shows a flyback configuration using the continuous conduction mode. The pin PROTECT is used in this example for external overtemperature protection and open loop or output short-circuit protection.
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Product data sheet
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NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
Vmains Vi
VCC GND PROTECT CTRL
1 2 3 4
8 DRAIN 7 6 5 DRIVER power MOSFET Rss Css Rsense
TEA1532BT TEA1532CT
SENSE
DEM
RCTRL
RDEM
coa050
Fig 9. Flyback configuration using the discontinuous conduction mode
TEA1532BT_TEA1532CT_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 18 January 2007
16 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
Vi
Vi drain of power MOSFET
VO
Vstartup VCC
Vth(UVLO)
VDRIVER
2.5 V VPROTECT
start-up sequence
normal operation
OVP TEA1532CT
normal operation
output short-circuit TEA1532CT
brown-out(1)
001aaf069
(1) In CCM, the brown-out protection is implemented by the maximum duty cycle in combination with pin PROTECT.
Fig 10. Typical waveforms 1
TEA1532BT_TEA1532CT_1
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Product data sheet
Rev. 01 -- 18 January 2007
17 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
Vi
Vi VDRAIN
VO
Vstartup VCC Vth(UVLO)
VDRIVER
2.5 V VPROTECT(1)
start-up sequence
normal operation
protection active(2)
001aaa841
(1) When VPROTECT is forced above 3 V, the protection is always latched. So the IC is not started at Vstartup unless the VCC voltage drops below the VVCC(latch)(reset) level. This is the same action used for external OTP compensation described in Section 7.15. (2) External OTP for TEA1532BT and TEA1532CT; OVP and output short circuit for TEA1532BT.
Fig 11. Typical waveforms 2
TEA1532BT_TEA1532CT_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 18 January 2007
18 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
Vmains Vi
VCC GND PROTECT(1) CTRL Rslopecomp RCTRL
1 2 3 4
8 DRAIN 7 6 5 DRIVER power MOSFET Rss Css Rsense
TEA1532BT TEA1532CT
SENSE
DEM
coa051
(1) The pin PROTECT is used in this example for external OTP and open loop or output short-circuit protection. Slope compensation is determined by the value of Rslopecomp.
Fig 12. Flyback configuration using the continuous conduction mode
12. Test information
12.1 Quality information
The General Quality Specification for Integrated Circuits, SNW-FQ-611 is applicable.
TEA1532BT_TEA1532CT_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 18 January 2007
19 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
13. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
D
E
A X
c y HE vMA
Z 8 5
Q A2 A1 pin 1 index Lp 1 e bp 4 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.041 0.228 0.016 0.024
8o o 0
ISSUE DATE 99-12-27 03-02-18
Fig 13. Package outline SOT96-1 (SO8)
TEA1532BT_TEA1532CT_1 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 18 January 2007
20 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
14. Revision history
Table 6. Revision history Release date Data sheet status Product data sheet Change notice Supersedes Document ID
TEA1532BT_TEA1532CT_1 20070118
TEA1532BT_TEA1532CT_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 18 January 2007
21 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. GreenChip -- is a trademark of NXP B.V.
16. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
TEA1532BT_TEA1532CT_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 18 January 2007
22 of 23
NXP Semiconductors
TEA1532BT; TEA1532CT
GreenChip II SMPS control IC
17. Contents
1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 8 9 10 11 12 12.1 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Distinctive features . . . . . . . . . . . . . . . . . . . . . . 1 Green features . . . . . . . . . . . . . . . . . . . . . . . . . 1 Protection features . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Start-up, mains enabling operation level and undervoltage lock out . . . . . . . . . . . . . . . . . . . . 6 Supply management. . . . . . . . . . . . . . . . . . . . . 6 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Cycle skipping. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current control mode . . . . . . . . . . . . . . . . . . . . 6 OverCurrent Protection (OCP) . . . . . . . . . . . . . 7 Demagnetization (QR operation) . . . . . . . . . . . 7 Valley switching. . . . . . . . . . . . . . . . . . . . . . . . . 7 Continuous Conduction Mode (CCM). . . . . . . . 8 Adjustable slope compensation . . . . . . . . . . . . 8 Minimum and maximum on-time. . . . . . . . . . . . 9 Soft start-up (pin SENSE). . . . . . . . . . . . . . . . . 9 Control pin protection . . . . . . . . . . . . . . . . . . . 10 PROTECT and timing input . . . . . . . . . . . . . . 10 OverTemperature Protection (OTP) . . . . . . . . 11 Brown-out protection. . . . . . . . . . . . . . . . . . . . 11 Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal characteristics. . . . . . . . . . . . . . . . . . 12 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13 Application information. . . . . . . . . . . . . . . . . . 15 Test information . . . . . . . . . . . . . . . . . . . . . . . . 19 Quality information . . . . . . . . . . . . . . . . . . . . . 19 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Contact information. . . . . . . . . . . . . . . . . . . . . 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 January 2007 Document identifier: TEA1532BT_TEA1532CT_1

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